The present invention relates to a process for producing a MOS-type semiconductor device and a MOS-type semiconductor integrated circuit device.
FIG. 16A is a sectional view of a conventional MOS capacitor element. It is used as a capacitor element of a circuit in a MOS-type or CMOS-type semiconductor integrated circuit device (hereinafter referred to sometimes as "IC").
Since this element is often formed in the same step as the gate oxide film of the MOS transistor of IC, a dielectric film (SiO.sub.2 film in this case) which is used as a capacitor is called, for convenience, a gate oxide film (gate SiO.sub.2 or gate Ox) 160001. Likewise, an electrode of the capacitor is called a gate electrode (polysilicon gate electrode or gate Poly) 160003. 160002 refers to a region of the gate oxide film (active), 160004 refers to a LOCOS oxide film (LOCOS SiO.sub.2 or LOCOS Ox) for separation of elements, 160005 refers to a P.sup..+-. -type field dope region for separation of elements (BFD region), and 160006 refers to a P-type (from 2 to 3 .OMEGA..multidot.cm, from 20 to 30 .OMEGA..multidot.cm) semiconductor substrate. For simplicity, an intermediate insulation film, a wiring metal and the like are omitted.
FIG. 16B is a plan view of FIG. 16A. In this pattern, an active size 160007 is 500 .mu.m.
FIG. 17A is a sectional view of a MOS capacitor element and FIG. 17B is a plan view of FIG. 17A. In a LOCOS oxide film 170004, an active region 170001 is divided into plural islands, which is a structure capable of stressing an influence of a LOCOS edge 170007 (influence on an dielectric breakdown voltage or yield). It is called an "island structure" hereinafter.
Meanwhile, a pattern shown in FIG. 16A is called a "plate pattern".
170004 is a BFD region, 170005 is a substrate, and 170006 is a size (500 .mu.m) of an outermost peripheral active portion (LOCOS edge).
The gate insulation films of the capacitor element and the MOS transistor should both withstand an upper limit (Vdd Max.) of a maximum operational voltage of IC's. Considering TDDB (time dependence dielectric breakdown: durability), a screening test is carried out. For instance, in the case of a product with Vdd Max. of 5 V, the test is conducted at approximately 7 V; in the case of a product with Vdd Max. of 12 V, the test is conducted at approximately 16 V. What matters here is an insufficient dielectric breakdown voltage, namely, a bad dielectric breakdown voltage or yield, of such a gate insulation film of the capacitor or transistor.
In a gate insulation film in a product of 5 V, Gate Tox may be 150 .ANG. or more to adjust an electric field to 3M (mega) V/cm or less considering TDDB. However, in a gate insulation film in a product of 12 V, it has to be 400 .ANG. or more.
That is, for obtaining a necessary capacity value, the capacitor comes to have a large area, and the transistor also comes to have a large area for obtaining a necessary electric current driving ability. Accordingly, a yield becomes poor.
The above-mentioned patterns of the capacitor having the size of 500 .mu.m.sup..quadrature. (explanation is given through measurement using a test pattern as a monitor of an dielectric breakdown voltage of an oxide film) are arranged, in many cases, in the same semiconductor substrate (in a wafer) for the test. Statistically, a data obtained upon using 100 patterns/wafer may be said to be a reliable data.
In a conventional process for producing a general semiconductor device, a Si single crystal is taken up in the form of an ingot, and then sliced. The thus-sliced disc is called a "wafer". The wafer having usually an oxygen concentration of from 3.times.10.sup.17 /cm.sup.3 to 12.times.10.sup.17 /cm.sup.3 undergoes a 1st oxidation step (which is referred to as "1st Ox") and various other steps, and it is changed into a complete wafer having IC incorporated therein. This wafer is divided into chips (dice) in a dicing step, and is then completed through packaging (actual packaging). The above-mentioned steps in the wafer are called "wafer process" in particular, and are ordinarily carried out separately from the steps before or after these steps.
The 1st Ox in the wafer process is generally a first heat treatment step. The 1st Ox and the subsequent general steps of forming a MOS-type semiconductor device (of course, formation of a gate oxide film is conducted on the way) are included in the conventional method.
FIG. 18 is a graph showing a frequency distribution of cumulative number in measuring a dielectric breakdown voltage using a plate pattern of a gate oxide film prepared by the conventional method. The measurement is conducted many times in the wafer using the above-mentioned pattern. Gate Tox is 500 .ANG.. An intensity of an electric field is plotted as the abscissa for generalization. A unit is not described in the ordinate. This is because the graph is to show the state of the distribution. Mode A indicates a deficiency such as a phenomenon close to short-circuiting which is presumably ascribable in general to a dust or the like. Mode B indicates poor dielectric breakdown voltage which is presumably ascribable to an irregular film thickness. Mode C is a so-called intrinsic dielectric breakdown voltage which the oxide film has to exhibit inherently, and which is not deficient. It is ideal that all numbers are to be distributed in mode C (range of from 9 MV/cm to 10 MV/cm may be said to be an intrinsic dielectric breakdown voltage).
Generally, it is difficult to quantitatively discuss such a distribution because of the following parameters.
Dependency on an area (a large area is disadvantageous) PA1 Dependency on a pattern PA1 Dependency on a concentration of a substrate However, the discussion will be given on the basis of the above-mentioned conditions and limitations.
FIG. 19 is the same graph as that in FIG. 18 except that an island pattern is used. The distribution in the island pattern is inferior to that in the plate pattern.
FIG. 20 is a graph showing an average value of a dielectric breakdown voltage of a gate oxide film prepared by the conventional method in relation to dependency on a film thickness.
The values in the various patterns are based on the above-mentioned data.
It is found that the average value of the dielectric breakdown voltage shows the dependency on the film thickness, that the minimum point is provided in the region of from 400 to 500 .ANG. which should be used in IC to operate at 12 V as mentioned above and this is less advantageous, and that even if the thickness is increased to 700 .ANG. or 800 .ANG., the result is the same as in the thickness of 300 .ANG..
The results in the island pattern prove to be worse. In view of the area ratio alone, the total area of the island pattern is to be smaller than that of the plate pattern. Accordingly, this is not a mere problem with deficiency due to a dust or the like. This is presumably ascribable to a LOCOS edge.
As described above, in the conventional technique, the yield of the gate oxide film is poor, which influences the yield of IC. Especially, with the film thickness of 400 .ANG. or more, the yield is further decreased. In the pattern having the LOCOS edge, the yield is much worse.